Power dissipation of electronic circuits is becoming increasingly significant. Power consumption in sequential circuits is generally proportional to clock frequency. As designers continue to increase clock frequency in order to boost circuit performance, the power required to distribute the clock and drive the clock inputs of the sequential circuitry may account for a third or more of total chip power consumption. Dual edge triggered clocking schemes may be attractive because they allow a global clock to be distributed at half frequency. This reduction in clock frequency may result in significant power savings.
A challenge of dual edge triggered clocking schemes is that the sequential circuits (flip-flops, latches and other state holding elements) tend to be more complicated and can result in increased power consumption and/or slower devices. Dual edge triggered clocking schemes also tend to preclude phase-based designs such as transparent latches and/or traditional domino circuits. Yet another challenge in dual edge triggered clocking schemes is that the duty cycle of the clock generally has to be well controlled to avoid introducing additional skew on the falling edge of the clock.
What is needed are sequential circuits, or storage elements, that store data on both clock edges, thereby saving energy when distributing a clock signal. The merit of a sequential circuit may be measured by its efficiency with respect to power, latency and robustness given timing uncertainty. What is further needed are dual edge triggered flip flop circuits that employ pulsed latches to store data on both clock edges in a fast, efficient and robust manner.